Patented linearization and switched input buffer techniques ensure precise signal conversion and wide bandwidth at high speeds.
The post Imec Unveils 7‑bit, 175GS/s Massively Time-Interleaved Slope-ADC appeared first on Semiconductor Digest.
Imec Unveils 7-Bit, 175GS/s Massively Time-Interleaved Slope-ADC
At IEEE ISSCC 2026, imec revealed a groundbreaking 7-bit, 175GS/s ADC that combines a compact footprint with low energy consumption. This innovation addresses the growing demands of AI and cloud-driven data centers.
AI Summary
At IEEE ISSCC 2026, imec revealed a groundbreaking 7-bit, 175GS/s ADC that combines a compact footprint with low energy consumption. This innovation addresses the growing demands of AI and cloud-driven data centers.
FAQs
What is the significance of the 7-bit, 175GS/s ADC?
The ADC offers a compact design and low energy consumption, addressing the needs of AI and cloud data centers.
What technologies enable the ADC's performance?
It utilizes a novel linearization approach and switched input buffers to enhance signal integrity and efficiency.
What are the future plans for this ADC technology?
Imec is developing a 3nm follow-on design and exploring advanced nodes for improved performance.
How can companies collaborate with imec on this technology?
Imec invites partners to join their research programs, with options to license their underlying IP.
Where was the ADC unveiled?
The ADC was unveiled at the IEEE ISSCC 2026 conference.
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