The paper introduces RISCover, a framework designed to detect architectural vulnerabilities in closed-source RISC-V CPUs. Evaluated on multiple CPUs, it reveals previously unknown vulnerabilities, emphasizing the need for improved security analysis methods.
The paper “RISCover: Automatic Discovery of User-exploitable Architectural Security Vulnerabilities in Closed-Source RISC-V CPUs” was published by researchers at CISPA Helmholtz Center for Information Security.
Abstract “The open and extensible RISC-V instruction set has enabled many new CPU vendors...
The paper introduces RISCover, a framework designed to detect architectural vulnerabilities in closed-source RISC-V CPUs. Evaluated on multiple CPUs, it reveals previously unknown vulnerabilities, emphasizing the need for improved security analysis methods.
RISCover is a framework for detecting architectural vulnerabilities in closed-source RISC-V CPUs, focusing on user-exploitable bugs.
It compares instruction-sequence behavior across CPUs to identify deviations without needing source code or hardware modifications.
It identified four vulnerabilities, including GhostWrite and several halt-and-catch-fire bugs.
Closed-source CPUs pose challenges for vulnerability analysis, making it crucial to find and address potential security risks.
The technical paper can be accessed through the ACM Digital Library at the provided link.
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